Using the right methodology for applying and using products within a design project is critical to getting a high return on investment (ROI). This is especially true in emerging areas such as formal ...

Learn how using formal verification can take you beyond the limitations of directed-random simulation when debugging silicon. A series of case studies provide real-world usage examples of Jasper ...

Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications. Formal has been essential ...

Nothing is worse for a design team than a chip that fails to work in the bringup lab. Electrical problems are historically a major cause of such failures. Power leaks, power-ground DC paths, missing ...

This article is about our experience in applying formal verification techniques to an ASIC design in a large communication system. When we, in the Alcatel-Lucent IC design group in Nürnberg, Germany, ...

The automotive functional safety standard, ISO 26262, defines two verification requirements for integrated circuits used in automotive applications—systematic failure verification and random hardware ...

Driven by the need to objectively measure the progress of their verification efforts and the contributions of different verification techniques, IC designers have adopted coverage as a metric. However ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...