Semiconductor Engineering

UVM Register Layer: The Structure

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full ...
Design-Reuse

Unveiling Efficient UVM Register Modeling with IDesignSpec™ GDI by Agnisys®

In the field of semiconductor design and verification, the Universal Verification Methodology (UVM) is a key tool for achieving robust and efficient verification environments. At the heart of UVM lies ...
Design-Reuse

Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

Writing and reading registers is the primary way that the behavior of most IPs is controlled and queried. As a consequence of how fundamental registers are to the correct operation of designs, ...
Business Wire

Agnisys Offers Free Register Generator for UVM

SAN JOSE, Calif.--(BUSINESS WIRE)--Agnisys today announced a free version of its Hardware Specification tool – IDesignSpec™. It enables users to capture hardware specification that is automatically ...
Semiconductor Engineering

Accessing Registers With UVM-RAL

As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register ...