EDN

Product how-to: Reliable SoC bus architecture improves performance

This paper describes a modeling project to architect the bus topology and evaluate the read/write traffic patterns for a new multimedia System-On-Chip. Using the selected modeling and simulation ...
EDN

System performance analysis of an all programmable SoC block diagram

The performance of an SoC is measured at the device or system level, not at the interface or circuit block level. A primary component that determines performance is how effectively the system ...
Design-Reuse

Automated Architecture Checking of UML Based SoC Specifications

This paper documents work that has been carried out to automate the checking of system software architecture specifications of SoCs. Checking the architecture ...
Design-Reuse

Embedded DSP Software Design on a Multicore SoC Architecture: Part 1

Designing and building embedded systems is a difficult task, given the inherent scarcity of resources in embedded systems (processing power, memory, throughput, battery life, and cost). Various ...
HotHardware

Leaked AMD Mendocino Block Diagram Reveals Its Unique Chip Architecture

Hardware enthusiasts of a certain vintage will become misty-eyed and nostalgic when they hear the word "Mendocino." That might be exactly why AMD picked that codename for its own cut-down, low-cost ...