Electronic Design

Bulletproof Your System Timing With Programmable Clocks

Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if ...
Semiconductor Engineering

What Do Timing Constraints Have To Do With Clock Domain Crossing?

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality ...
Electronics Weekly

FPGA design improved by correct setting of clocks and timing constraints

In FPGA design, where timing is everything, there are tips and tricks to help designers set up clocks, correctly set timing constraints and then tune parameters of the FPGA, write Angela Sutton and ...
Electronic Design

Communications Timing: Pruning clock-tree problems

The interpretation of signals within a synchronous digital communications system relies upon timing. Whether a 1 or a 0 is read by a receiver depends entirely on when the signal is sampled, and sample ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
EDN

Advantages of timing networks with cesium atomic clocks

In a telecommunications network, every network element with synchronous intermachine links requires proper synchronization to minimize transport errors. A good example of synchronization is a network ...